rrTV-PHOTO   New HD TV
HOME   rrTV-PHOTO   GALLERIES   MY GALLERY   HELP-FAQ
myHOME PM pmRR MEMBERS 692 ONLINE 19 EVENTS SEARCH REGISTER  START HERE
 
12 pages [ <<    <     8      9     ( 10 )     11      12     NEXT    >> ]19268 viewsPOST REPLY
Boca Bearings . Modefo's RC Helicopters . XHELI.COM

.
.
Radio - Servo - Gyro - Gov - Batt > Homebrew PCM Receiver: QPSK/RF Design
 
 
MarkF
Senior Heliman
Location: Palo Alto, CA

Howdy!

It's probably obvious to most of you, but it's worth pointing out that the limits of latency here have little to do with processing speed. The Blackfin processor can execute a 512 point complex FIR filter in only about 1.6 microseconds! So, what's the deal with the 2.66 milliseconds that I've been complaining about?

There are two primary factors that contribute to latency during filtering operations. The first, obvious factor is the speed of the CPU itself. With the Blackfin, we've got processing power to burn - this truly is a great little chip for software-defined radio applications! CPU processing time is only a minor contributor to latency with this chip.

The second factor is even more important. The architecture of the filter determines how many samples from the past, and from the future, must be included in each filtering computation. With a 512-point FIR filter, it's easy: 256 previous samples must be included with 256 samples from the "future" to determine what the filtered output will be at each point in time. Unfortunately, this leads to a latency of 256 sample times at 96 KHz, or 2.66 mS.

One of the most important advantages of IIR filters is that they need a smaller number of samples (future and past) to do their job. On this project, every additional 96 KHz "future" sample that's required by the filter increases latency by ~10.4 microseconds. By choosing a filter that requires fewer samples to deliver the same RF performance, we can significantly reduce latency. IIR filters do complicate the situation somewhat, since they use feedback, which increases latency. Despite this, most IIR filters deliver a shorter "group delay" (latency) than an equivalent FIR filter can. Now, will we be able to design a bandpass IIR SRRC filter? Time will tell...

Cheers!
MarkF
10-05-2004 Over year old.
HOMEPAGE  
 
 
MarkF
Senior Heliman
Location: Palo Alto, CA

O, what a tangled web we weave...

Hello!

There's all sorts of interesting things happening around here. After corresponding back and forth with the author of Filter Solutions (& FilterFree), he sent me a note today explaining that he'd managed to work out the mathematics for bandpass SRRC filters, and that he'd be releasing a new version of Filter Solutions in the next few days that will add this capability! Whoa - now that's customer support! Kudos to Jeff Kahler for a superb job!

There's no question that Filter Solutions is a very powerful program. It can design IIR and FIR, digital, passive and active analog filters, diplexers, transmission lines, etc, etc, etc, in innumerable different permutations. It also performs group delay equalization to make IIR filters "more linear phase", quantization analysis for simulating those important real-world implementations, Z- and S-domain analysis and synthesis, and can spit out coefficients, schematics, netlists, or even complete C listings. Very impressive!

When the new version is released, we'll be able to answer the question definitively. Will a bandpass IIR SRRC filter deliver acceptably low latencies, even after group delay equalization? Your guess is probably better than mine is!

What'll make this even more complicated is that three hours before Jeff announced that he'd figured it out, I contacted the Guru of advanced signal processing himself, Fred Harris (author of the Multirate processing book I'd mentioned earlier). I doubt that it'll happen, but if we could get even an hour of Fred's time, our chances of success would increase dramatically. With Fred, you're always guaranteed to learn about new tricks, new methods, and flat-out better ways of doing things. I'll cross my fingers in hopes that he'll find this project interesting!

I have no bloody idea where we're going to wind up, but I'm sure enjoying the ride!

Have Fun!
MarkF
10-06-2004 Over year old.
HOMEPAGE  
 
 
MarkF
Senior Heliman
Location: Palo Alto, CA

Argh!

Hi, Gang!

I've learned two things over the past day or so while trying to dive in and learn Eagle. First, while Eagle is a usable PCB design package, it isn't very efficient for non-standard components - or at least I'm not!

The second thing I've learned is to think at least twice before launching into designing a new library component. After spending a good 3-4 hours last night and this morning defining the package, symbol, and component definitions for the LMX2313U PLL chip that I'd done all the simulation on, it finally dawned on me that this teeny little 3.5mmx3.5mm chip-scale package is something that I can't build! Argh!!!

Sure, for enough money, you can build boards that use just about any kind of IC packaging, including chip-on-board direct wire bonding. However, for prototyping purposes, this tiny little package blows past all the rules for the standard PCB prototyping shops. I suspect that I wouldn't even be able to get the board fabbed, much less be able to solder this little critter down.

And as Murphy would expect, this PLL is only available in this package!

Oh, goody, we get to start all over again! I think I'm learning something - just very slowly...

Best Regards,
MarkF

P.S. On the other hand, I am going to have to figure this out eventually, since the 22V10 is in the same situation. It can only hit the necessary operating frequency when it is packaged in a similar QFN package. Perhaps it's time to find a high-tech fab shop? $$$ - sigh.
10-08-2004 Over year old.
HOMEPAGE  
 
 
azaparov
Heliman
Location: Boston,MA

get LMX2331
it's dual chip but IF part is good from 45 to 510 Mhz. Available in tssop package.
10-08-2004 Over year old.
 
 
MarkF
Senior Heliman
Location: Palo Alto, CA

Hi, Azaparov!

That's an excellent idea! I hadn't seen another alternative from National that would do the job, because I'd only been looking for single PLL chips. The LMX2331 does look like a very strong candidate, even if we aren't using the other PLL. I'm sure that other companies such as Analog Devices have viable alternatives, but I'm hooked on the ease of use of National's WEBENCH PLL Simulator.

As I'm learning, there's a big difference between the LMX2313's SLD20a package and the 22V10a's QFN package. The problem with the SLD20a is that the package's contacts are completely buried beneath the chip, so the only way to go is with IR reflow. Fortunately, the QFN package (while obviously designed for reflow soldering) has contacts that wrap around the edge of the package slightly, making it possible for a talented technician (that wouldn't be me!) to solder it down without needing the tooling for the solder stencil that's used for IR reflow.

So, it sounds as though we may be able to get back into a buildable state by changing from the LMX2313 to the LMX2331, just as you suggest. Thank you very much for the great recommendation!

Cheers!
MarkF
10-09-2004 Over year old.
HOMEPAGE  
 
 
MarkF
Senior Heliman
Location: Palo Alto, CA

Hi, Gang!

As I've been playing around with different PLL designs using the LMX2332U (the lower frequency version of the LMX2331), my thoughts keep coming back to the VCO's output harmonics. Unfortunately, I don't know what they're like - i.e. the relative strength of the even harmonics versus the odd harmonics. For the sake of argument, let's imagine that they are comparitively equal, with the amplitudes decreasing normally with increasing frequency.

Thinking about the goal of the VCO in this case, the ideal output would be a square wave - the sum of the odd harmonics. If we were to design a "perfect" filter for the VCO, the output would instead be a sine wave. So, the question is this: is there a simple analog filter topology that acts like a comb filter? In other words, if it were possible, it would be cool to be able to design a filter that eliminated only the even harmonics of the VCO, which would give us the "squarest" output pulse shape. This would reduce the jitter induced by the input sampling process in the PLD, which would be quite handy.

Now, I suspect that this might be possible at a single frequency, but it probably isn't possible in the analog domain over a wide frequency range. If anyone knows of a way to pull this off, though, it would be great to hear about it!

On other topics, I'm now trying to decide where to draw the boundaries of how much to implement on the L.O. test PCB. What keeps nagging at me is that if I were to just add the input transformer, QuickSwitches, sampling caps, and an audio amplifier, we'd actually have a functional low-sensitivity receiver! I'd skip the RF preamp and bandpass filter, since that'll take a lot more work, but this is tempting. The problem is that it may be a lousy performer thanks to the jitter induced by PLD clocking, which could make the additions a waste of time. On the other hand, this would also give me a good chance to prototype the audio amp, under the assumption that it'll probably need tweaking in a second pass.

What do you think? Should I focus solely on the synthesizer and PLD, or is it worth expanding this a bit to get a "Rev 0" receiver implementation? I'm also very interested in knowing your thoughts as to whether I should include a VCO output filter in this pass or not. I'd love to hear what you think - thanks a bunch!

Cheers!
MarkF
10-09-2004 Over year old.
HOMEPAGE  
 
 
Bezjak
Heliman
Location: Boca Raton, FL

Mark,

I don't know of any way to get rid of just the even harmonics. So, one option is to simply use the VCO output without filtering. Harmonics which are present may be the result of the signal not having a 50% high, 50% low waveform (50% duty cycle). If the duty cycle is not 50%, then your quickswitches will be spending more time in one position than the others. I don't know if this is a big deal in your architecture, but I think it would introduce an imbalance between the I and Q channels.

You can get closer to a 50% duty cycle by filtering out ALL of the harmonics, and leave yourself a sine wave. I doubt that driving your logic with a sine wave will degrade your jitter performance since the dv/dt rate for a 300 MHz sine wave near it's midpoint is pretty fast even without the third harmonic. I routinely drive a Motorola 145170 with a sine wave at much lower frequencies (between 5 and 70 MHz), and I get excellent phase noise performance from the logic. In my case, (and I think in yours) phase noise is dominated by the VCO characteristics, not the logic.

I would build just the synthesizer portion with lots of test connectors to get from the board to your nifty new network analyzer or a good scope. Then, once you are confident of the design, you can drop it into the complete receiver design without the test connectors. You probably want to be able to break out the VCO output, as well as each of the four PLD outputs, so that you can check their spectral purity.

Just my 2 cents,
Greg
10-09-2004 Over year old.
 
 
MarkFSenior Heliman - Location: Palo Alto, CA -
Hi, Greg!

That's exactly what I wanted to know! I've been worried that the phase noise would be too high - you're post is very reassuring! I've been making such slow progress in Eagle that I had to take a break and see what an appropriate VCO output filter design would look like. My "quick break" turned into several hours of playing around with dozens of different filter designs, and I think I may have a candidate filter for the VCO output. Here's the design: a 6-pole passive elliptic filter:



As it turned out, what took the most time was trying to get the insertion loss as low as possible given realistic part 'Q' (quality of merit) figures. As you can see above, I'm assuming Qs of 30, which is hopefully pretty reasonable. Here's the resulting frequency response:



While it's a little hard to see, Filter Solutions predicts a loss at 312 MHz of about just 1.2 dB, which is quite acceptable for this application.

So, I'll definitely follow your suggestions. The L.O. test PCB will stay just that, and I'll add the test connectors that you've recommended. I really appreciate your feedback, Greg! Thank you very much for the advice!

Have Fun!
MarkF
10-10-2004 Over year old.
HOMEPAGE  
 
 
MarkF
Senior Heliman
Location: Palo Alto, CA

Howdy, Folks!

I've got some good news and some bad news. Good news first. A bit more thinking has revealed an interesting point: duty cycle isn't very important here! Since the quadrature clock outputs are just a divide-by-four of the VCO, we only care about the frequency of the drive clock, rather than its duty cycle. This suggests that we may not have to implement the rather serious VCO filter shown above, and may be able to do something quite a bit simpler. Excellent!

Now the bad news. The one significant disadvantage of National's dual-PLL chips is that they've lost the ability to use a crystal, and instead require an external oscillator. Now, that wouldn't be so bad, except that the FCC mandates a 20 ppm frequency accuracy specification for our rigs, and standard crystal oscillators offer either 50 ppm or 100ppm accuracy. Achieving 20 ppm is normally accomplished in R/C radios by adjusting a trimmer capacitor. With off-the-shelf integrated oscillators, however, the only parts that I've seen that offer a trimmer are TCXOs (Temperature Compensated Xtal Oscillators) that are more expensive than the Blackfin CPU!!! As a consequence, we'll have the choice of buying an even more expensive TCXO, or adding yet another chip to build an oscillator from scratch.

Fortunately, 10 MHz oscillators aren't all that difficult to build, but this will mean that an entirely new source of phase noise will need to be taken care of, in addition to the need for more homebrewed shielding, etc. OK - there's more work to do!

So, the ongoing process of discovery continues!

Have Fun!
MarkF
10-10-2004 Over year old.
HOMEPAGE  
 
 
azaparov
Heliman
Location: Boston,MA

TXCO

This is the 2.5ppm oscillator I have been using with great success:
Digikey part: 300-1105-1-ND

OSC TCXO 16.800MHZ 3.0V SMD

They have different frequencies.
10-10-2004 Over year old.
 
 
MarkF
Senior Heliman
Location: Palo Alto, CA

Hi, Azaparov!

Not bad - that's the most attractive TCXO that I've seen. Small, low power, accurate, and it supports frequency adjustment via an external pot - it looks great! For the sake of making more forward progress, I'll use this part, even though it is nearly as expensive as the Blackfin. I guess that I'll be blowing my BOM cost targets! The two areas where I've compromised on costs so far are the VCO and TCXO. Fortunately, these are both areas that are obvious choices for future cost reduction, where more design time and sweat equity could pull out at least $5-6.

I really appreciate your taking the time to help me out - thank you!!!

Cheers!
MarkF
10-10-2004 Over year old.
HOMEPAGE  
 
 
Bezjak
Heliman
Location: Boca Raton, FL

Mark,

Sorry about sending you off track on the duty cycle. I am used to thinking about VCOs directly driving double balanced mixers. Of course when you divide by four, all of the action happens on one VCO clock edge.

However, what if you DID clock your logic on both edges?

I am thinking about 2 separate divide-by-2 flip flops circuits. One is driven by CLK, the other is driven by an inversion of CLK. Now the CLK frequency only has to be 150 MHz instead of 300 MHz. These two circuits would end up generating two 75MHz signals 90 degrees out of phase.

Just to check that I wasn't way out of line, I did a search and found the same idea at http://www.holmea.demon.co.uk/Ethernet/EthernetRx.htm
I think you would have to add an inverter to the CLKI signal in that schematic to equalize the delays.

This gets you out of your bind with the physical package of the 22V10. It could be implemented with glue logic parts. (Actually it can't be implemented on the 22V10 since he only has 1 clock input).

The Fairchild NC7SV74 is a high speed flip flop which could fit the bill. His max clock freq is 200MHz and it's only $.30.

Just a thought...
Greg
10-10-2004 Over year old.
 
 
MarkF
Senior Heliman
Location: Palo Alto, CA

Hi, Greg!

My goodness - no apologies are necessary! Quite to the contrary, I've learned a lot about analog filter design in the last day or so! As I'm sure everyone's noticed, I'm not in much of a hurry on this project. Since my first goal is to learn, each "diversion" is an opportunity to gain a better understanding of the space. As a case in point, your feedback about direct clocking working fine was certainly a relief, but your comments about duty cycle were in many ways even more valuable to me. Once I realized that the consequences of inclusion of the various harmonics could be viewed as duty cycle variation, then it made it possible to be a lot less worried about filter quality, to the point where I may well just try building the L.O. test board without any filter at all.

Most recently, I've been discovering what a challenge it'll be creating a sharp 72-73 MHz bandpass filter. While this is getting rather ahead of the game, sharp passive filters appear to be a no-go for the rejection that I'm targeting. Instead, I've found that active filters seem to be much more controllable. The most promising filter that I've found so far is a 6-8 pole Chebyshev I bandpass filter in a positive SAB filter topology (as a bandpass filter, this really has 12 or 16 poles). Most of the other filter types wound up creating fF caps (femto!) and the like, which I'm definitely not going to try to build!

Your recommendation for the dual-clocking approach is definitely a cool one, and if I weren't so far along with the current architecture, it would certainly be worth serious consideration! Since I've already got the VCOs on the way, though (including a possible custom 200 MHz version), I think I'm committed to this approach for now. However, if the VCO board turns out poorly, this'll be a worthy backup plan. Thanks for coming up with it!

On another topic, I remember earlier when you'd mentioned that you were curious how the canned VCOs performed. I just realized in context that my experiments probably won't help you out much, unfortunately. The challenge is that the Premier VCOs aren't particularly clean. Their standard parts spec at -95 dBc/Hz phase noise at 10 KHz, versus 100 dB for some other suppliers. In addition, I consciously chose to accept an extra 5 dB of phase noise when I moved to the higher power output of the V-0305-05 component (-90 dB phase noise), in an attempt to improve the odds of the direct clocking approach working properly. I suspect that this is well below the performance regime that you're accustomed to working in - sorry about that!

Even so, as I periodically go in and tweak the synthesizer simulation, we're starting to get pretty decent overall synthesizer performance. At the moment, the best result that I've seen has an RMS phase error of 0.84 degrees at 300 MHz, which is just fine from my perspective. At the QuickSwitches, it should be lower due to the "divide-by-four" implementation. As long as the PLL direct clocking scheme works out OK, the RMS phase noise at 75 MHz should be less than 0.3 degrees - not bad at all! I'm not certain of this, but I seem to recall a paper from a while back that claimed that an RMS phase error of 0.3 degrees was roughly equivalent to a 0.1 dB SNR degradation as compared to a "perfect" oscillator. If so, I'll be a very happy camper!

Thanks again for your help!!!

Cheers!
MarkF
10-10-2004 Over year old.
HOMEPAGE  
 
 
MarkF
Senior Heliman
Location: Palo Alto, CA

Hi, Folks!

Whoops! The more I think about my last post, the more I think that I was doing OK right up there until the end. If I'm even remembering correctly, the 0.3 degree / 0.1 dB SNR relation applied to symbol timing recovery in a baseband QPSK signal, which sufficiently describes the problem. Applying this to an L.O. oscillator in an unspecified system ranks right up there with trying to quantify deciliters / furlong or farts / megahertz. Oops!

The problem is that L.O. jitter affects far more than symbol timing recovery. Most importantly, it disperses all the input signal frequencies by the error associated with the jitter. In this case, that means that everything that the receiver sees will be getting randomly "smeared out" by about 40-45 Hz. That will in turn introduce a variety of sources for error, all of which will contribute to SNR degradation. In fact, those sources would be quite complex to predict, so I can't even say if this is an acceptable level of phase noise or not.

My apologies, folks. I must be learning something, because at least I can spot my stupid mistakes a little more often. Now, if only I could learn to do that before I say anything...

Have Fun!
MarkF
10-10-2004 Over year old.
HOMEPAGE  
 
 
Bezjak
Heliman
Location: Boca Raton, FL

Mark,

For HF, the best preselection filters we use have 30dB of attenuation at a 10% frequency offset. Unfortunately, they also have 8dB of loss. For example see http://www.jps.com/downloads/PDFS/pps100.pdf

Don't pay attention to the 35dB min. attenuation number. For the PPS-100 in the real world, it is 30dB.

I don't know exactly which filter topology they use. I can find out if you are interested and you think you can tolerate the loss.

I don't think you will be happy with an active filter in your front end. I would expect the noise figure to be pretty high. I have no idea what the IP3 and desense performance would be... I just haven't seen it done.

When you are targeting best strong signal performance, it is best not to have any active components before the first mixer if you can possibly avoid it.

For your application, I would go with a filter topology similar to what is found on homebrew ham receivers. See http://www.arrl.org/tis/info/pdf/001009qex013.pdf for a pretty good article on RF filters. This is the very similar to the topology used on the RF filter for the old ACE R/C Silver Seven kit receiver.

Good luck,
Greg
10-11-2004 Over year old.
 
 
MarkFSenior Heliman - Location: Palo Alto, CA -
Hi, Greg!

Ah-hah! No wonder I've found it to be a bit of a challenge to find the right filter design! Here's the frequency response of the filter that I described above. I apologize that you can't see the frequency range in the chart due to a bug in Filter Solutions, but this is plotted from 71 MHz to 74 MHz - the center 50% is the active R/C band, and the "flat" (1 dB ripple) passband is actually 1.3 MHz wide (the 1.3 MHz filter passband was chosen so that the group delay variation in the "real" 1 MHz passband is less than 800 nS, so that it won't impact QPSK's linear-phase requirement to any significant degree). I've got two versions of this filter: the other one offers +20 dB of gain, with essentially identical frequency response. As you can see, this plot of the 8 (/16) pole filter shows that I've been shooting for 90 dB of attenuation at a ~1.3% frequency offset!!! Maybe I ought to chill out a little!?!



Your advice on the front-end is very much appreciated! There are, however, a couple of areas that need special treatment in QSD-based receivers as compared to traditional RF gear. The original SDR-1000 was just as you describe: it contained a front-end passive bandpass filter, and then the RF input went directly into the QuickSwitches (through a 1:4 transformer). After folks got more experience with the rig, Gerald discovered that he needed to redesign the front-end, and the reason was the switching noise of the QuickSwitches. By placing a high-performance Sirenza SGA-4586 SiGe RF preamp on the front-end (included on the new "RFE" board that's part of all new SDR-1000s), sensitivity and noise floor have improved dramatically, as has DR3! This isn't an isolated instance: the HF Circuits and Systems book I mentioned earlier also emphasizes that direct conversion receivers require RF preamps, while also pointing out that most conventional (superheterodyne) SSB receivers don't use them.

It actually makes sense, especially for R/C. Since our antennas don't have a well-defined impedance, at a minimum, we'll need a front-end buffer amp so that the bandpass filter will see a controlled impedance level; otherwise, the bandpass filter won't work properly. So, I've been toying with the idea of creating an active bandpass filter, where the Sirenza is the active element of the first stage of the filter. Based on your feedback, it does sound like I ought to perhaps relax my performance expectations a tad!

We're definitely marching into new territory here, where experiments are genuine research. Thanks to your feedback, perhaps we can find a common middle ground that offers the best of both worlds!

Thanks again, Greg!

Cheers!
MarkF
10-11-2004 Over year old.
HOMEPAGE  
 
 
MarkF
Senior Heliman
Location: Palo Alto, CA

Hi, Greg!

A bit more playing around has shown me just how heroically difficult it would be to build that filter above (I'd misunderstood some of the options in Filter Solutions), so we'll obviously need to back off on the target performance. However, this discussion strikes at the heart of the problem. In a superhet, you have the benefit of performing filtering at intermediate frequencies, but with this architecture, there isn't an I.F.! With the QSD, we either have to filter at RF, or at baseband prior to the A/D.

The A/D itself gives us some help from 96 KHz to 3.072 MHz, but we've got to be very careful to ensure that we don't get input overranging, in which case the A/D can't do a thing. In other words, we've really just got the RF filter and the baseband filter to get rid of any strong interferers. There's obviously a limit to the usefulness of baseband filtering; even if we tried to perform 100% of the filtering at baseband, the QSD itself will alias at harmonics and subharmonics of the carrier frequency. As a result, I believe that the QSD will require a better RF filter than the typical "prescaler" filter. Your feedback makes it clear, though, that I ought to seek to minimize the filtering at RF to what's truly necessary, and to move the rest to baseband.

Thus far, I've just been playing around with designing filters, trying to see how good I could make them. It sounds like the next step is to spend more time determining how best to distribute the filtering between RF and baseband. Hmmm - time to go and learn more! Thanks again for helping to keep this pointed in the right direction!

Cheers!
MarkF
10-11-2004 Over year old.
HOMEPAGE  
 
 
MarkF
Senior Heliman
Location: Palo Alto, CA

Hi, Greg!

By the way, thank you for pointing out the filter design article! I decided to look for the software that the author had mentioned, Radio Designer, and it's no longer available. Apparently it morphed into a package called Serenade, and morphed again into Ansoft Designer, which is now one of the top RF design packages out there. Since they've got a student version available, this might be worth checking out.

Do you by any chance use Ansoft Designer at work?

Best Regards!
MarkF
10-11-2004 Over year old.
HOMEPAGE  
 
 
Bezjak
Heliman
Location: Boca Raton, FL

Mark,

Actually, we use ARRL Radio Designer. We bought it years ago, and it was the best $150 we ever spent. It was really Super-Compact with the microstrip elements removed. Since we don't do microstrip filters or matching circuits, it wasn't a problem for us.

The Ansoft product looks like it is descended from Super-Compact. I can see this is so in the report (plot) user interface. It is not all that intuitive, so it takes a bit of patience.

I just downloaded the SV version to take a look at it. I looks like you get all the functionality that Radio Designer had, plus schematic entry, plus more component types, and the price is right.

It's kinda cool that you are doing all of this legwork finding neat new radios and software. I have been out of the RF world for a couple of years. I took a detour into land of audio switching, DSPs, DSL, and T1/E1 stuff. I am just getting back into RF work in the last couple of months.

Later,
Greg
10-12-2004 Over year old.
 
 
MarkF
Senior Heliman
Location: Palo Alto, CA

Hi, Greg!

Hallelujah! I'm delighted that you've been able to find something useful in this pile of sh...aving cream (do you remember Dr. Demento? )! Seriously, you've been very helpful, indeed - I'm a lot happier if I can return a tiny bit of the favor!

It's been an interesting day! Jeff Kahler, the author of Filter Solutions, let me be the alpha tester for the new release today that includes bandpass SRRC FIR filters (still no bandpass SRRC IIR filters yet, but this is nonetheless terrific progress). I did find a couple of issues, and Jeff turned around and corrected them within an hour! Kudos, indeed, for absolutely tremendous support. I'm seriously impressed with Filter Solutions and Jeff - we will definitely be buying at least one real copy at work. I also played with Ansoft briefly this morning; if you'd appreciate a truly interactive filter design program, play with Filter Solutions! 20 Day evaluations are free - you don't even have to register. That's what makes Jeff's support even more impressive - I'm currently just a freeloader!

Jeff also made an excellent suggestion as we exchanged emails: he emphasized that SRRC filters are pulse-shaping filters, not attenuation filters, and that the best combination might be to serially combine a high-attenuation filter with an SRRC filter. That's a superb idea! I'll have to play with this tomorrow to see what kind of latency reductions we'll be able to get using just FIR filters. Down the road, hopefully Jeff will also implement IIR bandpass SRRC filters, so that we'll be able to make that comparison, too!

Have Fun!
MarkF
10-12-2004 Over year old.
HOMEPAGE  
 
 
12 pages [ <<    <     8      9     ( 10 )     11      12     NEXT    >> ]19268 viewsPOST REPLY
Autography FlightPower . Advantage Hobby . Revolution Models

.
.
Radio - Servo - Gyro - Gov - Batt > Homebrew PCM Receiver: QPSK/RF Design
 PRINT TOPIC Advertisers 

Subscribe to This Topic

Tuesday, December 2 - 4:29 am - Copyright © 2000 - 2008 runryder.com | email | link to rr | runryder needs cookie